Integrated circuit (IC) complexity has been increasing in accordance with Moore's law for several decades, approximately doubling the number of digital gates in a device every two years or less. This exponential rise in gate counts has resulted in rapidly escalating test complexity and cost. This has, in turn, driven the industry to adopt design-for-test (DFT) approaches such as “scan test” to enable automated test pattern generation and efficient test application with lower cost production test equipment. Scan testing is an industry-standard structural test methodology that has proven to be a highly effective methodology for screening defective IC's in production.
FIG. 1 shows an abstracted view of an IC 100 containing both combinational logic 101, such as “AND”, “OR” and “NOT” gates, as well as memory elements 102 such as “flip-flops”. At opposing ends of the IC are functional inputs 104 and functional outputs 106. The resulting sequential logic circuit is more complicated to test because it can be difficult to construct an efficient sequence of input states to ensure all combinational and memory elements are fully stimulated and any defective responses are propagated to output pins. These problems are generally referred to as “controllability” and “observability”, respectively.
FIG. 2 shows the same abstracted IC 100 as FIG. 1, but with the addition of a test mode wherein all memory elements are connected into a simple serial shift register, known as a “scan chain” 200 having a scan input 202 and a scan output 204 at opposing terminals. Now the problem of controllability has been addressed, because all memory elements can be deterministically forced to any desired state, allowing control of all the inputs to the clouds of combinational logic. Also, the problem of observability has been addressed, because the value captured by all memory elements can be deterministically forced directly to the scan output pin 204.
Note that while FIG. 1 and FIG. 2 only show a small number of logic elements and input and output paths, a typical IC may contain millions of logic elements and hundreds of I/O pins. Also, while FIG. 2 shows separate device pins for functional and scan access, in a typical implementation, these pins will be shared using appropriate test-mode gating logic, such that a given pin may be used as a functional pin when the device is in functional mode, and the same pin may be used as a scan pin when in scan test mode.
Scan test data volume (i.e. stimuli and expected responses) grows with design size. In order to minimize test time and therefore test cost, scan data must either be shifted into and out of the device at higher speed, or with a higher degree of parallelism, or both. Shifting scan data at higher speeds adds design complexity, as it places tighter constraints on scan timing paths. Hence, the industry has generally adopted wider scan interfaces, with a typical deep sub-micron system-on-chip (SOC) device using dozens or even hundreds of parallel scan chains as shown conceptually in FIG. 3. The single scan chain 200 routed serially through every memory element in the design shown in FIG. 2 has been replaced with two separate scan chains 300, 301, each routed serially through half the memory elements 102 in the design. Each memory element 102 has the exact same degree of controllability and observability, but can be accessed with half the number of scan shift events. While the total volume of scan data has not been affected, it is being loaded and unloaded into the scan chains with twice the efficiency resulting in half the total test time and hence half the total test cost. A relatively simple IC with a parallel, full-scan design is shown in FIG. 4a. 
As noted previously, this a very simple, abstracted example. In a modern SOC device with millions of memory elements and hundreds or thousands of signal pins, the test and complexity and hence test cost can be much, much higher, driving a corresponding increase in parallelism.
To further reduce scan data volume and test cost, it is now common to implement some sort of on-chip circuitry to enable scan data compression. There are a variety of methodologies in this regard, but all methods share a common architecture, which is shown in abstracted form in FIG. 4b. Each scan chain 400 is broken up into a number of smaller scan chains 402 that are driven in parallel from a single scan input pin 404. The resulting scan chain outputs 406 are logically recombined, such as by using an XOR tree 408, before being driven to a single scan output pin 410. FIG. 4b shows a simple 2:1 compression ratio; however, much higher ratios are possible for devices incorporating very long scan chains.
Highly parallel scan testing has enabled reduced production test costs and hence improved product profitability. However, escalating design complexity and cost has resulted in a new set of challenges to the traditional scan architecture. Multi-product designs, wherein one IC is intended to be used in many target products or applications, as well as multi-die packaging technology such as MCM, SIP, and 3-D or stacked-die, have resulted in devices where some I/O pins may not be accessible for application of scan data in some package variants. This means a choice between compromised test coverage on some variants (due to not being able to access some scan chains), or increased test cost on all variants (due to constraining the design to use fewer, longer scan chains).
In extreme cases, package variants may not even be predictable at design time, meaning a high risk of future costs due to being forced either to connect otherwise unused pins to enable full scan coverage, or to redesign the IC to use fewer scan chains.
In a multi-product device with some pins not required in some target markets, there may be a desire to reduce package cost by not bonding out unused pins. There may also be other reasons not to connect all pins in the package, for example, to limit functionality in certain product variants to provide different price points to customers.
However, failure to connect certain pins in the package limits the selection of I/O's to be used for test purposes, hence limiting the degree of scan parallelism. In effect, the design team is forced to choose between using a small set of common pins for scan testing (resulting in high test cost), or being forced always to bond out a large number of pins in all cases for efficient scan test (resulting in high package cost and poor product differentiation).
FIG. 5 provides a graphical representation of this issue. In the abstracted product, certain I/O pins 500 are not available in package variants and therefore cannot be allocated to scan chains 502 (dashed lines). Consequently, the total number of scan chains 502 in the design is reduced, and the overall test time is increased for all package variants, not just the reduced-pin variant.
This predicament can be expected to escalate in the future, with the advent of even more complex and expensive packaging technologies, in particular multi-die packages such as multi-chip modules (MCMs), system-in-package (SIPs), stacked-die, etc. It will be critical to have very high test coverage at the bare-die level to ensure only good dies are included in assembled packages This necessitates highly parallel scan testing and hence very wide scan input and output buses. However, many or even most of the pins on some of the die in a multi-die package may only be connected to other die and hence may not be accessible for final package testing, meaning either package test coverage must be compromised due to not all scan chains being accessible, or overall test cost must be increased by only allowing a reduced set of the available pins on the die to be used for scan testing.
There is therefore a need to address some or all of the issues described above by enabling any number of pins to be used for scan testing at any stage in the design, without any loss of test coverage or a need to regenerate scan data.